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@anangl anangl commented Oct 6, 2025

This is a follow-up to commit f0f5f8c.

There is no need to check if TXE interrupt flag is set before calling tx_dummy_bytes(), as the function can handle the case when it is called even though there is no room in the TX FIFO. On the other hand, the check may be actually harmful, as it may prevent adding more items to the TX FIFO while the SSI controller is waiting until the FIFO achieves its transfer start level.

@anangl anangl added the bug The issue is a bug, or the PR is fixing a bug label Oct 6, 2025
@anangl anangl force-pushed the mspi_dw_fix_single_io_rx_isr_follow_up branch from f190c5c to 0ec325c Compare October 6, 2025 21:21
This is a follow-up to commit f0f5f8c.

There is no need to check if TXE interrupt flag is set before
calling tx_dummy_bytes(), as the function can handle the case
when it is called even though there is no room in the TX FIFO.
On the other hand, the check may be actually harmful, as it may
prevent adding more items to the TX FIFO while the SSI controller
is waiting until the FIFO achieves its transfer start level.
Remove the check then and exit the ISR loop when no dummy bytes
could be written into the TX FIFO.

Signed-off-by: Andrzej Głąbek <[email protected]>
@anangl anangl force-pushed the mspi_dw_fix_single_io_rx_isr_follow_up branch from 0ec325c to 112ee48 Compare October 6, 2025 21:23
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